A conventional technique exists where in a computer system, processing corresponding a device is executed at high speed by saving a process under execution by a central processing unit (CPU) in response to an interrupt signal from the device and by executing interrupt processing for the interrupt signal. Processing corresponding to the device is referred to as a device driver and device driver operations include a single-operation type driver executing one process for one interrupt signal and a continuous-operation type driver continuously executing processes for one interrupt signal.
The single-operation type driver makes a change to a software-friendly interface in response to a register set operation of a device. The single-operation type driver corresponds to a driver of a keyboard and a driver of a mouse, for example. The continuous-operation type driver sets direct memory access (DMA) to perform data transfer in response to an interrupt signal for a depletion or a buffer-full state of a buffer managed by First-In, First-Out (FIFO). The continuous-operation type driver corresponds to a driver of a display and a driver of a camera, for example.
The continuous-operation type drivers often have a deadline set by specifications for given data subject to the data transfer. For example, if a display is refreshed at 60 [Hz], the driver of the display has a specification of transferring data within a deadline of about 0.017 [seconds].
With regard to the form of implementation of interrupt processing in a multicore processor system equipped with multiple CPUs, for example, the interrupt processing is placed entirely on a master CPU among the CPUs and the master CPU executes all of the interrupt processing in one implementation form (this form will hereinafter be referred to as a conventional technique 1). In another form of implementation, the interrupt processing is distributed among CPUs and each of the CPUs executes the interrupt processing (this form will be referred to as a conventional technique 2).
For example, with regard to the conventional technique 2, a technique is disclosed where each CPU has a driver executing the interrupt processing and when interrupt occurs, the drivers arbitrate CPUs executing the interrupt processing (see, e.g., Japanese Laid-Open Patent Publication No. 2006-338184).
In another technique, for example, each CPU refers to a table having as a data structure, addresses of functions acting as interrupt processing and each CPU utilizes a semaphore mechanism of an operating system (OS) for using exclusion to execute the interrupt processing. A technique is disclosed that produces a memory saving effect in this way without placing the interrupt processing on all the CPUs (see, e.g., Japanese Laid-Open Patent Publication No. 2008-140191).
However, in the conventional techniques described above, the conventional technique 1 has a problem in that when the interrupt processing concentrates on the master CPU, the concentration of load causes the interrupt processing to exceed the period of time in which the interrupt processing should be processed, reducing response performance in real-time processing. The conventional technique 2 has a problem in that when an interrupt signal is generated, a sorting process is generated to determine which CPU executes the interrupt processing corresponding to the generated interrupt signal. The conventional technique according to Japanese Laid-Open Patent Publication No. 2008-140191 also has a problem in that although each CPU can execute the interrupt processing, the assignment of the interrupt processing to a CPU with a higher load may cause the interrupt processing to exceed the period of time in which the interrupt processing should be processed, reducing the response performance.